I have done a few internships which have resulted in different
projects, reports and occassionally papers. As most of this work has
happened over the last two years there is no clear distinction between
past and present projects.
- Automata theoretic verification of hybrid systems.
- A GUI for the B theorem prover.
- Design and verification of distributed reactive systems.
- Automated interface synthesis for System-on-Chip protocols.
- (past) Formal verification of industrial designs.
- Academic guest with David Basin. Chair of
Information Security, ETH Zurich.
- Academic guest with Bertrand Meyer. Chair of
Software Engineering, ETH Zurich.
- Research assistant with S. Ramesh. CFDVS, IIT Bombay.
- Visiting academic with Arcot Sowmya. School of
Computer Science and Engineering, University of New South Wales.
I have been an intern at Texas Instruments Bangalore in Rubin Parekhji's group
on three ocassions.
- Interface synthesis for a bus protocol. November - December 2003.
- Model checking a cache controller. January - June 2002.
- Model checking experiments with small Finite State Machines. May - July 2001.
My DBLP Entry.
- A Toolset for Modeling and Verification of GALS
S. Ramesh,Sampada Sonalkar, Vijay D'silva, N. Chandra and
B. Vijayalakshmi. 16th International Conference on Computer Aided
Verificationu (CAV), 2004, Boston.
- Synchronous Protocol Automata: A Framework for Modelling and
Verification of SoC Communication Architectures.
Vijay D'silva, S.
Ramesh, Arcot Sowmya. Design Automation and Test in Europe 2004, Paris.
- Bridge Over Troubled Wrappers: Automated Interface
Vijay D'silva, S. Ramesh, Arcot Sowmya. 17th International Conference on VLSI Design, Mumbai,